Scratchpad memory vs cache code#
In this method, data that is about to be accessed frequently is copied into the scratch pad using compiler-inserted code at fixed and infrequent points in the program. We propose a dynamic allocation methodology for global and stack data and program code that (i) accounts for changing program requirements at runtime, (ii) has no software-caching tags, (iii) requires no runtime checks, (iv) has extremely low overheads, and (v) yields 100p predictable memory access times.
Scratchpad memory vs cache full#
It is easy to see why a data allocation that never changes at runtime cannot achieve the full locality benefits of a cache. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior. A second category of algorithms partitions variables at compile-time into the two banks. Such methods incur large overheads in runtime, code size, energy consumption, and SRAM space for tags and deliver poor real-time guarantees just like hardware caches. Instructions are inserted before each load/store to check the software-maintained cache tags. First, software-caching schemes emulate the workings of a hardware cache in software. Primarily scratch pad allocation methods are of two types. It is motivated by its better real-time guarantees versus cache and by its significantly lower overheads in energy consumption, area, and overall runtime, even with a simple allocation scheme.
A scratch pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. T Ishihara and H Yasuura : A power reduction technique with object code merging for application specific embedded processors, Proceedings of Design Automation and Testing, Europe Conference (DATE 2000), March 2000.Abstract: In this research, we propose a highly predictable, low overhead, and, yet, dynamic, memory-allocation strategy for embedded systems with scratch pad memory.J Kin, M Gupta and WH Mangonie-Smith : The filter cache: An energy efficient memory structure, IEEE Micro-30 December 1997.Luca Benini, Alberto Macii, Enrico Macii, Massino Poncino : Synthesis of application specific memories for power optimisation in embedded systems, DAC 2000 Los Angeles, California, pp 300-303.Rajeshwari M Banakar, Ranjan Bose, M Balakrishnan : Low power design - Abstraction levels and RTL design techniques, VLSI test and design Workshop, VDAT 2001 Bangalore, Aug 2001 Google Scholar.Rajeshwari Banakar, S Steinke, B S Lee, M Balakrishnan and P Marwedel, Comparison of cache and scratch pad based memory system with respect to performance, area and energy consumption, Technical Report 762, University of Dortmund, Sep 2001.S Wilton and Norm Jouppi : Cacti : An enhanced access and cycle time model, IEEE Journal of Solid State Circuits, May 1996.Schlager : DSPStone : A DSP-oriented benchmarking methodology, In Proceedings of the 5th International Conference on Signal Processing Applications and Technology, October 1994. Preeti Ranjan Panda, Nikhil Dutt, Alexandru Nicolau : Memory issues in embedded systems on-chip - Optimisations and exploration, Kluwer Academic Publishers, 1999.Doris Keitel-Sculz and Norbert Wehn., Embedded DRAM Development Technology, Physical Design, and Application Issues, IEEE Design and Test of Computers, Vol 18 Number 3, -15, May/June 2001.
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